1. Field of the Invention
The present invention relates to an image processing system for generating images in accordance with image information to generate images based upon the image generating signals. The invention also relates to a method for controlling such system.
2. Related Background Art
In conjunction with FIG. 19 to FIG. 21, the description will be made of one example of the image processing system for generating images in accordance with image information.
FIG. 20 is a view which illustrates an image generating system (hereinafter referred to as an engine) 101 centering on its inner structure. At first, the laser beams that emitted from a semiconductor laser 901 are incident upon a polygon mirror 903 through an f.theta. lens 902. By means of the polygon mirror 903, the laser beams are caused to scan on a photosensitive drum 905 of through a cylindrical lens 904. Also, the laser beams from the polygon mirror 903 are reflected on a BD mirror 906, and detected as BD signals by means of a BD detection circuit 907. Then, images are written on the photosensitive drum 905 on the basis of the BD signals 104 from the BD detection circuit 907.
In FIG. 19, the BD signals 104 transmitted from the engine 101 are received by the control circuit 802 of an interface unit 801. The control circuit 802 generates the LSYNC signals 106 to be transmitted to the image generating system 803; the resetting signal WRST (write reset) 111 to the FIFO memory 805; the RRST (read rest) 112; and the clock PCLK 113 in synchronism the BD signals 104. Also, this circuit is provided with the PWM IC 110 that performs the PWM conversion of the multivalued image data to make them binary image data in order to provide the gradations for one dot.
The image generating system 803 comprises an image memory 806 and a driver 807. In synchronism with the arbitrary clock (hereinafter referred to as "VCLK") 804, one-line portion of the multivalued image data VIDEOA1 is transferred from the image memory 806 to the driver 807, and in turn, from the driver 807 to the interface unit 801. However, the clock VCLK 804 is assumed to generate a frequency higher than the frequency at which the one line portion of image data is transferred within a period of BD cycle.
Now, the description will be made of the operation to be performed under the system thus arranged. At first, in synchronism with the clock VCLK 804 transmitted by the image generating system 803, one line portion of the multivalued image data VIDEOA1 is written on the FIFO memory 805 in the interface unit 802. The one line portion of the multivalued image data VIDEOA1 is read out in synchronism with the image clock PCLK 113 serving as the image generating signals. Thus, this portion of the data is transferred to the PWM IC 110. This PWM IC 110 binalizes the multivalued image data VIDEOA2 and converts them into the binary image data VDO.
Then, with the image clock PCLK 113 which is also inputted into the PWM IC, the binary image data VDO is transferred to the semiconductor laser 901 in the engine 101 in synchronism with the image clock PCLK 113, thus generating images.
FIG. 21 is a timing chart which shows each of the signals generated in the control circuit 802 of the interface unit 801. The VIDEOA1 and VIDEOA2 are 8-bit multivalued image data. The multivalued image data VIDEOA2 are the data written between the intervals of the last BD signal, and read out between the intervals of the next BD signal. This set up is the same in the description to be made later. Then, at the timing of the LSYNC signal 106, the multivalued image data VIDEOA1 are swept out from the image generating system 803, and the binary image data VDO are transferred to the engine 101 in synchronism of the BD signal 104.
The transfer speed of the one line portion of the image data to be sent out from the image generating system 803 to the FIFO memory 805 in the interface unit 801, namely, the clock VCL, is dependent on the cycle of the BD signal of the engine 101. This transfer speed should be set so as to enable the one line portion of the image data to be transferred within the period of one cycle of the BD signal 104.
However, there is a limit to the transfer speed made available by the clock VCLk even if the provision of a higher speed is attempted for the image clock PCLK 113 of the engine 101. Here, due to this limit, a problem is encountered that system cannot be built as desired.